---- 1Hz Clock --------------------------------------
entity clk_div is
port(clk_27MHz : in std_logic; -- 27MHz 입력
clk_1Hz : out std_logic ); -- 1Hz 출력
end clk_div;

architecture sample of clk_div is
begin
process(clk_27MHz)
variable cnt : integer range 0 to 13499999;
variable clk_out : std_logic;
begin
if clk_27MHz"event and clk_27MHz="0" then
if cnt < 13499999 then
cnt := cnt + 1;
elsif cnt=13499999 then
cnt := 0;
clk_out := not clk_out; --반주기마다 clk_out 을 토글 시킴
end if;
end if;
clk_1Hz <= clk_out;
end process;
end sample;