LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY ripple_up_7seg IS
PORT (CONTROL, CLK_27MHZ : IN STD_LOGIC;
Q : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
SEG_OUT: OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
END ripple_up_7seg;

ARCHITECTURE Structure OF ripple_up_7seg IS
COMPONENT T_FF
PORT (T, CLK : IN STD_LOGIC;
Q, NQ : BUFFER STD_LOGIC);
END COMPONENT;
COMPONENT clk_div is
port(clk_27MHz : in std_logic; -- 27MHz 입력
clk_1Hz : out std_logic ); -- 1Hz 출력
END COMPONENT clk_div;
COMPONENT seven_seg is
port(bcd: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(13 downto 0));
END COMPONENT seven_seg;

SIGNAL NQ : STD_LOGIC_VECTOR(2 DOWNTO 0);
SIGNAL CLK_1HZ : STD_LOGIC;

BEGIN
c0 : clk_div port map(CLK_27MHZ, CLK_1HZ);
U0 : T_FF PORT MAP(CONTROL,CLK_1HZ,Q(0));
NQ(0) <= NOT Q(0);
U1 : T_FF PORT MAP(CONTROL,NQ(0),Q(1));
NQ(1) <= NOT Q(1);
U2 : T_FF PORT MAP(CONTROL,NQ(1),Q(2));
NQ(2) <= NOT Q(2);
U3 : T_FF PORT MAP(CONTROL,NQ(2),Q(3));
S0 : SEVEN_SEG PORT MAP(Q, SEG_OUT);
END Structure;


---- T F/F -----------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY T_FF IS
PORT (T, CLK : IN STD_LOGIC;
Q, NQ : BUFFER STD_LOGIC);
END T_FF;

ARCHITECTURE Structure OF T_FF IS
BEGIN
PROCESS(CLK)
BEGIN
IF(CLK"EVENT AND CLK="1") THEN
IF T = "1" THEN
Q <= NOT Q;
END IF;
END IF;
END PROCESS;
END Structure;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

---- 1Hz Clock --------------------------------------
entity clk_div is
port(clk_27MHz : in std_logic; -- 27MHz 입력
clk_1Hz : out std_logic ); -- 1Hz 출력
end clk_div;

architecture sample of clk_div is
begin
process(clk_27MHz)
variable cnt : integer range 0 to 13499999;
variable clk_out : std_logic;
begin
if clk_27MHz"event and clk_27MHz="0" then
if cnt < 13499999 then
cnt := cnt + 1;
elsif cnt=13499999 then
cnt := 0;
clk_out := not clk_out; --반주기마다 clk_out 을 토글 시킴
end if;
end if;
clk_1Hz <= clk_out;
end process;
end sample;

---- 2digit 7seg decoder --------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity seven_seg is
port(bcd: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(13 downto 0));
end seven_seg;

architecture sample of seven_seg is
begin
process(bcd)
begin
case bcd is
when "0000" => seg <= "11111111000000";
when "0001" => seg <= "11111111111001";
when "0010" => seg <= "11111110100100";
when "0011" => seg <= "11111110110000";
when "0100" => seg <= "11111110011001";
when "0101" => seg <= "11111110010010";
when "0110" => seg <= "11111110000011";
when "0111" => seg <= "11111111011000";
when "1000" => seg <= "11111110000000";
when "1001" => seg <= "11111110011000";
when "1010" => seg <= "11110011000000";
when "1011" => seg <= "11110011111001";
when "1100" => seg <= "11110010100100";
when "1101" => seg <= "11110010110000";
when "1110" => seg <= "11110010011001";
when "1111" => seg <= "11110010010010";
when others => seg <= "11110011111111";
end case;
end process;
end sample;