LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

Entity Shift_reg1 Is
Port(Pin_in, CLK : In std_logic;
Pin_out : Out std_logic;
Q : Buffer std_logic_vector(3 downto 0));
End Shift_reg1;

Architecture Exm_Model Of Shift_reg1 Is
Component D_FF
Port( D, CLK : In std_logic;
Q : Out std_logic);
End Component;
Begin
U3: D_ff Port Map(Pin_in,CLK,Q(3));
U2: D_ff Port Map(Q(3),CLK,Q(2));
U1: D_ff Port Map(Q(2),CLK,Q(1));
U0: D_ff Port Map(Q(1),CLK,Q(0));
Pin_out <= Q(0);
End Exm_Model;

--------- D F/F -------------------------------
LIBRARY ieee;
Use ieee.std_logic_1164.all;

Entity D_FF Is
Port(D, CLK : In std_logic;
Q : Out std_logic);
End D_FF;

Architecture Exm_Model Of D_FF Is
Begin
Process(CLK,D)
Begin
If CLK"EVENT and CLK="1" Then
Q <= D;
End If;
End Process;
End Exm_Model;