LIBRARY ieee;
USE ieee.std_logic_1164.all;

Entity gp_register Is
Port(SEL: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
IN_SR, IN_SL : IN STD_LOGIC;
CLK : IN STD_LOGIC;
I : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A : BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0));
End gp_register;

Architecture Exm_Model Of gp_register Is
COMPONENT MUX4_1
Port(I0,I1,I2,I3 : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
F : OUT STD_LOGIC);
End COMPONENT;
COMPONENT D_FF
Port(D, CLK : In std_logic;
Q : Out std_logic);
End COMPONENT;

SIGNAL Sig_m : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
M3: MUX4_1 PORT MAP(A(3), IN_SR, A(2), I(3), SEL, Sig_m(3));
M2: MUX4_1 PORT MAP(A(2), A(3), A(1), I(2), SEL, Sig_m(2));
M1: MUX4_1 PORT MAP(A(1), A(2), A(0), I(1), SEL, Sig_m(1));
M0: MUX4_1 PORT MAP(A(0), A(1), IN_SL, I(0), SEL, Sig_m(0));
D3: D_FF PORT MAP(Sig_m(3), CLK, A(3));
D2: D_FF PORT MAP(Sig_m(2), CLK, A(2));
D1: D_FF PORT MAP(Sig_m(1), CLK, A(1));
D0: D_FF PORT MAP(Sig_m(0), CLK, A(0));
End Exm_Model;


--------- MUX 4X1 -------------------------------
LIBRARY ieee;
Use ieee.std_logic_1164.all;

Entity MUX4_1 Is
Port(I0,I1,I2,I3 : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
F : OUT STD_LOGIC);
End MUX4_1;

Architecture Exm_Model Of MUX4_1 Is
BEGIN
WITH S SELECT
F <= I0 WHEN "00", -- NO CHANGE
I1 WHEN "01", -- SHIFT RIGHT
I2 WHEN "10", -- SHIFT LEFT
I3 WHEN OTHERS; -- PARALLEL REGISTER
END Exm_Model;


--------- D F/F -------------------------------
LIBRARY ieee;
Use ieee.std_logic_1164.all;

Entity D_FF Is
Port(D, CLK : In std_logic;
Q : Out std_logic);
End D_FF;

Architecture Exm_Model Of D_FF Is
Begin
Process(CLK,D)
Begin
If CLK"EVENT and CLK="1" Then
Q <= D;
End If;
End Process;
End Exm_Model;