실습파일
-- Clock Division ----------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity CLK_DIV is
port(clk_50MHz : in std_logic; -- 27MHz 입력
clk_1Hz : out std_logic ); -- 10Hz 출력
end CLK_DIV;

architecture sample of CLK_DIV is
begin
process(clk_50MHz)
variable cnt : integer range 0 to 24999999;
variable clk_out : std_logic;
begin
if clk_50MHz"event and clk_50MHz="0" then
if cnt < 24999999 then
cnt := cnt + 1;
elsif cnt = 24999999 then -- 1/5000000 분주
cnt := 0;
clk_out := not clk_out; -- 반주기마다 clk_out 을 토글 시킴
end if;
end if;
clk_1Hz <= clk_out;
end process;
end sample;