module parallel_register2(D, Q, CLK, PR, CLR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input CLK, PR, CLR;
input [3:0] D;
output [3:0] Q;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;

reg [3:0] D_reg;

assign HEX7 = 7"b1111111;
assign HEX6 = 7"b1111111;
assign HEX5 = 7"b1111111;
assign HEX4 = 7"b1111111;
assign HEX3 = 7"b1111111;
assign HEX2 = 7"b1111111;
assign HEX1 = 7"b1111111;

always @(posedge CLK or negedge CLR or negedge PR) begin
if(!CLR)
D_reg <= 4"b0000;
else if(!PR)
D_reg <= 4"b1111;
else
D_reg <= D;
end

assign Q = D_reg;
seg_decoder_4_7 Digit_A(Q, HEX0);

endmodule


//########################################
module seg_decoder_4_7 (B, H);
input [3:0] B;
output [6:0] H;

reg [6:0] HOUT;

assign H = HOUT;

always @ (B)
case(B)
4"b0000 : HOUT = 7"b1000000;
4"b0001 : HOUT = 7"b1111001;
4"b0010 : HOUT = 7"b0100100;
4"b0011 : HOUT = 7"b0110000;
4"b0100 : HOUT = 7"b0011001;
4"b0101 : HOUT = 7"b0010010;
4"b0110 : HOUT = 7"b0000011;
4"b0111 : HOUT = 7"b1111000;
4"b1000 : HOUT = 7"b0000000;
4"b1001 : HOUT = 7"b0011000;
4"b1010 : HOUT = 7"b0001000;
4"b1011 : HOUT = 7"b0000011;
4"b1100 : HOUT = 7"b1000110;
4"b1101 : HOUT = 7"b0100001;
4"b1110 : HOUT = 7"b0000110;
default : HOUT = 7"b0001110;
endcase
endmodule