module shift_register_serial_adder(AIN, BIN, AOUT, BOUT, CLK, PR, CLR, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7);
input CLK, PR, CLR;
input AIN, BIN;
output AOUT, BOUT;
output [6:0] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, HEX6, HEX7;

wire [3:0] S_TEMP;
reg [6:0] H1;

assign HEX7 = 7"b1111111;
assign HEX5 = 7"b1111111;
assign HEX3 = 7"b1111111;
assign HEX2 = 7"b1111111;

// 4 비트 두 수(A, B)를 직렬 전송하기 위한 Shift 레지스터
SHIFT_REG SR_A();
SHIFT_REG SR_B();

// 두 shift 레지스터의 출력 값을 더해주는 가산기
full_adder FA();
D_FF D0();

// 합의 결과를 담아 두는 레지스터
D_FF bit3();
D_FF bit2();
D_FF bit1();
D_FF bit0();

// 입력 값 및 합의 결과를 표시하기 위한 세븐세그먼트 디코더
seg_decoder_4_7 Digit_A(AOUT, HEX6);
seg_decoder_4_7 Digit_B(BOUT, HEX4);
seg_decoder_4_7 Digit_S(S_TEMP, HEX0);

// 최종 캐리의 값에 따라 한자리 또는 두 자리수의 HEX 값 출력
always @ (QOUT)

assign HEX1 = H1;

endmodule

//######## Shift-Register ########################
module SHIFT_REG(DIN, QOUT, CLK, CLR);
input CLK, CLR;
input DIN;
output QOUT;

wire [3:0] Q_TEMP;

D_FF bit3 (CLK,DIN ,CLR,Q_TEMP[3]);
D_FF bit2 (CLK,Q_TEMP[3],CLR,Q_TEMP[2]);
D_FF bit1 (CLK,Q_TEMP[2],CLR,Q_TEMP[1]);
D_FF bit0 (CLK,Q_TEMP[1],CLR,Q_TEMP[0]);

assign QOUT = Q_TEMP[0];

endmodule

//########### D-F/F ###############################
module D_FF(clk, d, rb, q);
input clk, d, rb;
output q;

reg q;

initial begin
q <= 0;
end

always @(posedge clk or negedge rb)
begin
if(rb==0) //if(!rb)
q <= 0;
else
q <= d;
end
endmodule

//#####################################
module full_adder(a, b, cin, sum, cout);
input a, b, cin;
output sum, cout;
wire temp_sum, temp_c1, temp_c2;

half_adder u0(a, b, temp_sum, temp_c1);
half_adder u1(temp_sum, cin, sum, temp_c2);
or u2(cout, temp_c1, temp_c2);
endmodule

//#####################################
module half_adder(a, b, sum, cout);
input a, b;
output sum, cout;
wire cout_bar;

xor U0(sum, a, b);
nand (cout_bar, a, b);
not U1(cout, cout_bar);
endmodule


//########################################
module seg_decoder_4_7 (B, H);
input [3:0] B;
output [6:0] H;

reg [6:0] HOUT;

assign H = HOUT;

always @ (B)
case(B)
4"b0000 : HOUT = 7"b1000000;
4"b0001 : HOUT = 7"b1111001;
4"b0010 : HOUT = 7"b0100100;
4"b0011 : HOUT = 7"b0110000;
4"b0100 : HOUT = 7"b0011001;
4"b0101 : HOUT = 7"b0010010;
4"b0110 : HOUT = 7"b0000011;
4"b0111 : HOUT = 7"b1111000;
4"b1000 : HOUT = 7"b0000000;
4"b1001 : HOUT = 7"b0011000;
4"b1010 : HOUT = 7"b0001000;
4"b1011 : HOUT = 7"b0000011;
4"b1100 : HOUT = 7"b1000110;
4"b1101 : HOUT = 7"b0100001;
4"b1110 : HOUT = 7"b0000110;
default : HOUT = 7"b0001110;
endcase
endmodule