module part5_1(SW, LEDR, HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0);
input [17:0] SW;
output [17:0] LEDR;
output [6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0;

assign LEDR = SW;
wire [2:0] Ch_Sel, Ch1, Ch2, Ch3, Ch4, Ch5, Blank;
wire [2:0] H4_Ch, H3_Ch, H2_Ch, H1_Ch, H0_Ch;

assign Ch_Sel = SW[17:15];
assign Ch1 = SW[14:12];
assign Ch2 = SW[11:9];
assign Ch3 = SW[8:6];
assign Ch4 = SW[5:3];
assign Ch5 = SW[2:0];

mux_3bit_5to1 M4();
mux_3bit_5to1 M3();
mux_3bit_5to1 M2();
mux_3bit_5to1 M1();
mux_3bit_5to1 M0();

char_7seg H7(Blank, HEX7);
char_7seg H6(Blank, HEX6);
char_7seg H5(Blank, HEX5);
char_7seg H4(H4_Ch, HEX4);
char_7seg H3(H3_Ch, HEX3);
char_7seg H2(H2_Ch, HEX2);
char_7seg H1(H1_Ch, HEX1);
char_7seg H0(H0_Ch, HEX0);

endmodule


// --- wide 3bit 5X1 MUX
module mux_3bit_5to1();
input [2:0] S, U, V, W, X, Y;
output [2:0] M;
wire [1:3] m_0, m_1, m_2;

// 5-to-1 multiplexer for bit 0
assign m_0[1] = (~S[0] & U[0]) | (S[0] & V[0]);
assign m_0[2] = (~S[0] & W[0]) | (S[0] & X[0]);
assign m_0[3] = (~S[1] & m_0[1]) | (S[1] & m_0[2]);
assign M[0] = (~S[2] & m_0[3]) | (S[2] & Y[0]);

// 5-to-1 multiplexer for bit 1
assign m_1[1] = (~S[0] & U[1]) | (S[0] & V[1]);
assign m_1[2] = (~S[0] & W[1]) | (S[0] & X[1]);
assign m_1[3] = (~S[1] & m_1[1]) | (S[1] & m_1[2]);
assign M[1] = (~S[2] & m_1[3]) | (S[2] & Y[1]);

// 5-to-1 multiplexer for bit 2
assign m_2[1] = (~S[0] & U[2]) | (S[0] & V[2]);
assign m_2[2] = (~S[0] & W[2]) | (S[0] & X[2]);
assign m_2[3] = (~S[1] & m_2[1]) | (S[1] & m_2[2]);
assign M[2] = (~S[2] & m_2[3]) | (S[2] & Y[2]);
endmodule

//------ seven segment decoder for H,E,L,O
module char_7seg(C, Display);
input [2:0] C;
output [6:0] Display;

wire [2:0] C;

assign Display[0] = ~(~C[2]&C[0]);
assign Display[1] = ~((~C[2]&~C[1]&~C[0]) | (~C[2]&C[1]&C[0]));
assign Display[2] = ~((~C[2]&~C[1]&~C[0]) | (~C[2]&C[1]&C[0]));
assign Display[3] = ~((~C[2]&C[0]) | (~C[2]&C[1]));
assign Display[4] = ~(~C[2]);
assign Display[5] = ~(~C[2]);
assign Display[6] = ~(~C[2]&~C[1]);
endmodule